This tender invites qualified consortiums to deliver an Upskilling Training Program focused on semiconductor IC chip design and verification in Central Punjab, under the Pakistan Software Export Board. The program targets fresh engineering graduates and industry professionals, aiming to bridge the skills gap in Pakistan's semiconductor ecosystem through a structured 4-month, 500-hour curriculum. The training covers foundational digital design, RTL coding with Verilog, ASIC design flow, SystemVerilog verification, and UVM methodology, delivered via hands-on labs and project-based learning. Training centers must be located within Central Punjab, equipped with EDA tools and labs, ensuring industry-aligned, job-ready skills. The program emphasizes practical exposure, industry mentorship, and post-training placement support. Bidders must comply with PEC and FBR requirements, including valid tax status and consortium agreements. The program demands a minimum technical score of 70% for financial proposal consideration. The financial proposal should detail per trainee costs inclusive of trainers, labs, software, and materials, excluding stipends. Submission deadline is set for 22nd April 2026 at 3:00 PM, with bid opening at 3:30 PM. Proposals must be submitted electronically via EPADS portal. Physical address for correspondence is Pakistan Software Export Board, 6th Floor New State Life Building, Blue Area, Islamabad. Pro-Tip: Ensure your consortium includes a local partner with presence in Central Punjab and submit all mandatory affidavits and financial documents on time to avoid disqualification. Also, carefully separate technical and financial proposals as per instructions to maintain eligibility.